1. Field of the Invention
The present invention relates to a latch circuit, more particularly, it relates to a latch circuit used as a component element such as a data processor integrated in a semiconductor substrate.
2. Description of the Related Art
In interconnection between a register for holding data, a latch circuit for holding the content of the register temporarily, an arithmetic unit and so on in a data processor integrated in a semiconductor substrate, such configuration that two signal lines of positive logic and negative logic in one signal is frequently adopted in order to simplify the circuit.
FIG. 1 is a schematic block diagram snowing a state where the register, latch circuit, arithmetic unit and so on are interconnected with the two signal lines of positive logic and negative logic. This configuration itself is same as that in the present invention to be described later.
In FIG. 1, numeral 1 designates a register, numeral 2 designates a latch circuit holding an output signal of the register 1 temporarily, and numeral 3 designates an arithmetic unit which inputs an output of the latch circuit 2 and the other signal not shown so as to perform an arithmetic operation. An output of the operation result by the arithmetic unit 3 is feedback to and stored into the register 1.
Characters 4a, 4b respectively show an X signal line of positive logic and a /X signal line of negative logic for sending the content of the register 1 as a signal X to the latch circuit 2. Characters 5a, 5b respectively show a Q signal line of positive logic and a /Q signal line of negative logic for sending an output of the latch circuit 2 as a signal Q to the arithmetic unit 3. Characters 6a, 6b respectively show an S signal line of positive logic and a /S signal line of negative logic for sending an output of the arithmetic unit 3 as a signal S to the register 1.
The X signal line 4a is of positive logic and the /X signal line 4b is of negative logic. Thus, it means that a value of the signal X is "1" when the X signal line 4a is of logic "1" and the /X signal line 4b is of logic "0", and the value of the signal X is "0" when the X signal line 4a is of logic "0" an the /X signal line 4b is of logic "1".
Also, the Q signal line 5a is of positive logic and the Q signal line 5b is of negative logic. Thus, it means that a value of the signal Q is "1" when the Q signal line 5a is of logic "1" and the /Q signal line 5b is of logic "0", and that the value of the signal Q is "0" when the Q signal line 5a is of logic "0" and the /Q signal line 5b is of logic "1".
Furthermore, the S signal line 6a is of positive logic and the /S signal line 6b is of negative logic. Thus, it means that a value of the signal S is "1" when the S signal line 6a is of logic "1" and the /S signal line 8b is of logic "0", and that the value of the signal S is "0" when the S signal line 6a is of logic "0" and the /S signal line 6b is of logic "1".
FIG. 2 is a circuit diagram specifically showing a conventional configuration of a portion corresponding to 1 bit of the register 1, latch circuit 2, X signal line 4a, /X signal line 4b, Q signal line 5a and /Q signal line 5b shown in FIG. 1. That is, the practical circuit as shown in FIG. 1 is realized by arranging the circuit configuration shown in FIG. 2 in parallel by the number of bits required.
In FIG. 2, characters 1a, 1b designate inverters in which respective outputs and inputs are connected. Characters 1c, 1d designate N-type FETs. A source electrode of the N-type FET 1c is connected to an output of the inverter 1a and an input of the inverter 1b, and a source electrode of the N-type FET 1d is connected to an input of the inverter 1a and an output of the inverter 1b. A portion corresponding to 1 bit of the register 1 shown in FIG. 1 is composed of the inverters 1a, 1b and the N-type FETs 1c, 1d.
Numerals 2a, 2b designate NAND gates in which respective outputs and first inputs are connected to constitute a Flip-flop 50. Numerals 2c, 2d, 2e and 2f respectively designate P-type FETs, whose source electrodes are connected to a source voltage Vcc.
Numerals 2g, 2h designate N-type FETs. Drain electrodes of the P-type FETs 2c, 2e and the N-type FET 2g are interconnected, and are also connected to a gate electrode of the P-type FET 2f and a second input, of the NAND gate 2a. Drain electrodes of the P-type FETs, 2d, 2f and the N-type FET 2h are interconnected, and are also connected to a gate electrode of the P-type FET 2e and a second input of the NAND gate 2b. A portion corresponding to 1 bit of the latch circuit 2 shown in FIG. 1 is composed of the NAND gates 2a, 2b, P-type FETs 2c, 2d, 2e, 2f and N-type FETs 2g, 2h.
Numerals 7a, 7b designate P-type FETs, whose source electrodes are connected to the source voltage Vcc.
A drain electrode of the N-type FET 1c, a source electrode of the N-type FET 2g and a drain electrode of the P-type FET 7a are connected to the X signal line 4a. A drain electrode of the N-type FET 1d, a source electrode of the N-type FET 2h and a drain electrode of the P-type FET 7b are connected to the /X signal line 4b. An output of the NAND gate 2a is connected to the /Q signal line 5b, and an output of the NAND gate 2b is connected to the Q signal line 5a.
Numerals 8, 9 and 10 respectively designate an RD control signal line, a /HLD control signal line and a /PCH control signal line. The RD control signal line 8 is the signal line of a signal RD for reading out a value from the register 1 and is connected to the gate electrodes of the N-type FETs 1c, 1d. The /HLD control signal line 9 is the signal line of a signal /HLD for making the latch circuit 2 hold a value, and is connected to the gate electrodes of the P-type FETs 2c, 2d and N-type FETs 2g, 2h. The /PCH control signal line 10 is the signal line of a signal /PCH for pre-charging the Q signal line 5a and the /Q signal line 5b, and is connected to the gate electrodes of the P-type FETs 7a, 7b.
Next, the operation of the conventional latch circuit and the register shown in FIG. 2 as mentioned above is described with reference to a waveform diagram of FIG. 3 showing variations of a voltage VX of the X signal line 4a and a voltage V/X of the /X signal line 4b.
In the state before transferring data to the latch circuit 2 from the register 1 composed of the inverters la, 1b and the N-type FETs 1c, 1d the RD control signal line 8, HLD control signal line 9 and /PCH control signal line 10 are of all logic "0". At this time, the N-type FETs 1c, 1d are in the non-conductive state, because the RD control signal line 8 is of logic "0". And hence, the inverters 1a, 1b are cutoff from the X signal line 4a and /X signal line 4b.
The P-type FETs 7a, 7b are in the conductive state, because the/PCH control signal line 10 is of logic "0". And hence, both the X signal line 4a and /X signal line 4b are precharged to logic "1".
The P-type FETs 2c, 2d are in the conductive state and the N-type FETs 2g, 2h are in the non-conductive state, because the /HLD control signal line 9 is of logic "0". Thus, since logic "1" is inputted to the second inputs of the NAND gates 2a, 2b, the flip-flop 50 composed of the NAND gates 2a, 2b holds the value at that time point. The P-type FETs 2e, 2f are in the non-conductive state, because logic "1" is inputted to the respective gate electrodes thereof.
The content of the register 1 is transferred to the arch circuit 2 by making the RD control signal line 8, /HLD control signal line 9 and /PCH control signal line 10 be logic "1". Hereupon, the value of the content of the register 1 is assumed to be "1". In other words, the inverter 1a is assumed to output logic "1" and the inverter 1b logic cause the RD control signal line 8 is of logic "1". Thus, electric charge on the /X signal line 4b, which is already precharged to logic "1", is discharged through the N-type FET 1d by the N-type FET of the inverter 1b which is outputting logic "0". And hence, the voltage V/X of the /X signal line 4b gradually falls from the voltage Vcc. Meanwhile, the X signal line 4a is kept at logic "1", because electric charge on the X signal line 4a, which is already precharged to logic "1", is not discharged.
When a drop in voltage VX of the /X signal line 4b becomes larger than a difference between the source voltage Vcc and a threshold voltage of an N-type FET, the N-type FET 2h becomes conductive. Thereby, electric charge of a signal line connected to the second input of the NAND gate 2b starts to flow out to the /X signal line 4b. Thus, the voltage starts to fall to the second input of the NAND gate 2b and, eventually, becomes lower than a threshold voltage Vth of the NAND gate 2b. At this time point or at a judgment point, the NAND gate 2b becomes in the state where logic "1" is outputted to the Q signal line 5a.
When a drop in voltage of the signal line connected to the second input of the NAND gate 2b becomes larger than a difference between the source voltage Vcc and a threshold voltage of the P-type FET, the P-type FET 2e becomes in the conductive state. Thereby, the signal line connected to the second input of the NAND gate 2a is prevented from becoming high impedance.
Meanwhile, since the X signal line 4a is kept at logic "1", an output of the NAND gate 2a becomes logic "0", because the logic "1" is still inputted to the second input of the NAND Mate 2a. Thereby, the data transfer to the latch circuit 2 from the register 1 is completed, because the Q signal line 5a becomes logic "1" and the /Q signal line 5b becomes logic "0".
In such a way, in the conventional latch circuit integrated on a semiconductor substrate, the input voltage to the second input of the NAND gate 2a or the NAND gate 2b constituting the internal flip-flop 50 starts to drop at the time point when a drop in the voltage VX of the X signal line 4a or the voltage V/X of the /X signal line 4b becomes larger than the difference between the source voltage Vcc and the threshold voltage of the N-type FET. The output of the NAND gate 2a or the NAND gate 2b constituting the flip-flop 50 becomes a desired state after the time point when the voltage VX of the X signal line 4a or the voltage V/X of the /X signal line 4b falls and becomes lower than the threshold voltage of the NAND gate 2a or the NAND gate 2b.
The falling speed of the voltage VX of the X signal line 4a or the voltage V/X of the /X signal line 4b is determined by a parasitic capacity of the X signal line 4a and the /X signal line 4b, and a driving capability of the N-type FET 1c and the N-type FET of the inverter 1a, or the N-type FET 1d and the N-type FET of the inverter 1b constituting the register.
In the data processor, though there are many portions which are constructed in such a manner as to interconnect the register for holding data, the latch circuit for holding the data temporarily and the arithmetic unit, particularly, in the portion such as a data path in which a number of registers are arranged, the above-mentioned parasitic capacity is very large and there is a limit to increase the driving capability of the N-type FET constituting the register and the N-type FET of the inverter from the view point of cost, and hence development of the high speed data processor is largely restricted.